Compact, Loadable 16- and 32-bit Binary Counters
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چکیده
Figure 1 is a block diagram representation of the I/O and architecture for a 16 or 32-bit counter. Pin CLK is the clock signal, RST the reset signal, and LOAD the load data signal. CLK is a positive, edge-triggered synchronous signal, and LOAD is an active low, synchronous signal. Pins D0 through D15, 31 are the load data inputs, and pins Q0 through Q15, 31 are the count bits. Pin Ci is the carry in; Co is the carry out. 4-bi t synchronous loadable binary counters are used to compose larger 16 or 32-bit counters. These 4-bit counters toggle on the rising edge of CLK when their RST is high and LOAD is low.
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